Since the invention of the personal computer, every iteration has grown more powerful and efficient.

Yet, as chip manufacturers squeeze billions of transistors onto each square centimeter of silicon, the fabrication process devours more and more power to make these transistors ever smaller.

“The energy it takes to physically manufacture a computer chip can be more than the chip consumes in its entire 10-year lifetime,” says Gage Hills, Assistant Professor of Electrical Engineering at the Harvard John A. Paulson School of Engineering and Applied Sciences.

That consumption from using chips is well-documented. Researchers at Lancaster University in the UK estimate that between 1.8 and 2.8 percent of global greenhouse gas emissions can be attributed to information and communications technologies such as data centers. The International Energy Agency predicts the sector’s electricity consumption could double between 2022 and 2026, rising to 4 percent of global demand, or roughly the same as used by Japan. This soaring need, Bloomberg reports, has slowed the retirement of coal-fired power plants.

Far less understood, however, is how to reduce the energy and environmental footprint of building the advanced chips that run those data centers and the large language models underpinning artificial intelligence.

A chip’s carbon footprint spans the length of the value chain, from mining the essential metals to the 1000-degree Celsius ovens used in the fabrication, to the lifetime energy use. The most advanced chips, moreover, house wires that are only 10 nanometers wide – about one-thousandth the diameter of a human hair. Defining such small features on the chip requires the use of high-energy photons with short wavelengths known as extreme ultraviolet (EUV) light. State-of-the-art EUV lithography processes account for a large share of modern computing’s carbon footprint.

With a seed grant from the Salata Institute for Climate and Sustainability at Harvard, Hills is investigating how to reduce emissions during production, and use, of next generation chips.  

“Now is the time where we can actually influence what is being developed, what will be used in the future, as opposed to trying to change existing processes at semiconductor manufacturing facilities,” says Hills, who runs the nano-design group at Harvard.

His timing is fortuitous. As existing fabrication processes are bumping against limits imposed by basic physics, new technologies are on the horizon.

“The two-dimensional shrinking of transistor devices, the driving principle behind Moore’s Law, is coming to an end,” says Hills. “The transistors just physically don’t work as well anymore once they get too small. As you make them smaller, we can no longer effectively control of the flow of electrons from one side of the transistor to the other, which makes our circuits much less energy efficient.”

Today’s computing systems are often comprised of many chips that are integrated on a circuit board. A large portion of their energy use is spent simply passing data back-and-forth between chips: transferring data from billions of tiny wires on one chip, to a mere hundreds of wires on a circuit board, and then back to billions of tiny wires on another tiny chip.

As Hills focuses on different approaches to chipmaking, he is researching which are the most environmentally efficient – and how to make those the industry standard.

For example, could multiple layers of integrated circuits be fabricated directly on top of each other, in three dimensions? That 3D integration could ease frictions transferring data between chips, since different layers of a single integrated circuit can communicate over billions of wires on the same chip. Unfortunately, however, this is very challenging with today’s silicon-based integrated circuits, because fabricating silicon transistors requires high temperatures: Try to make a layer of silicon circuits on top of an existing layer and you end up melting all the wires underneath. Instead, how about making transistors out of other types of semiconductors, including two-dimensional materials (such as graphene or transition-metal dichalcogenides), or carbon nanotubes (nano-scale cylinders of carbon atoms), which can be made at much lower temperatures? Such 3D-integrated chips could have lower overall carbon footprints, both during manufacturing and when the chips are in use.

Beyond the technical challenge, Hills says, is something more psychological: “Designers aren’t used to thinking about how much energy it takes to manufacture the chip, we typically think about how much energy they consume while they’re being used. We’re aiming for a paradigm shift in how designers create computer chips, where we consider their energy consumption and carbon footprint throughout their entire lifetime, including manufacturing.”